Rev: 1.11 8/2000

1/25

© 2000, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS88018/32/36T-11/11.5/100/80/66

512K x 18, 256K x 32, 256K x 36

8Mb Sync Burst SRAMs

100 MHz–66 MHz

3.3 V and 2.5 V I/O

100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

operation

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 100-lead TQFP package

Functional Description

Applications

The GS88018/32/36T is a 9,437,184-bit (8,388,608-bit for x32

version) high performance synchronous SRAM with a 2-bit

burst address counter. Although of a type originally developed

for Level 2 Cache applications supporting high performance

CPUs, the device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

The GS88018/32/36T is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88018/32/36T operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

from the internal circuit.

-11

-11.5

-100

-80

-66

Pipeline

3-1-1-1

tCycle

10 ns

4.0 ns

225 mA

10 ns

4.0 ns

225 mA

10 ns

4.0 ns

225 mA

12.5 ns

4.5 ns

200 mA

15 ns

5 ns

185 mA

Flow

Through

2-1-1-1

tCycle

11 ns

15 ns

180 mA

11.5 ns

15 ns

180 mA

12 ns

15 ns

180 mA

14 ns

15 ns

175 mA

18 ns

20 ns

165 mA