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GS88018T-11I датащи(PDF) 10 Page - GSI Technology

номер детали GS88018T-11I
подробное описание детали  512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
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Rev: 1.11 8/2000
10/25
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88018/32/36T-11/11.5/100/80/66
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.


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