GS88018/32/36BT-333/300/250/200/150

Rev: 1.04 2/2005

5/24

© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TQFP Pin Description

Symbol

Type

Description

I

Address field LSBs and Address Counter preset Inputs

A

I

Address Inputs

I/O

Data Input and Output pin

NC

—

No Connect

BW

IByte Write—Writes all enabled bytes; active low

I

CK

I

Clock Input Signal; active high

GW

I

Global Write Enable—Writes all bytes; active low

I

Chip Enable; active low

I

Chip Enable; active high

G

I

Output Enable; active low

ADV

I

Burst address counter advance enable; active low

ADSP, ADSC

I

Address Strobe (Processor, Cache Controller); active low

ZZ

I

Sleep Mode control; active high

FT

I

Flow Through or Pipeline mode; active low

LBO

I

Linear Burst Order mode; active low

I

Core power supply

I

I/O and Core Ground

I

Output driver power supply