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GS88136T-11I датащи(PDF) 7 Page - GSI Technology

номер детали GS88136T-11I
подробное описание детали  512K x 18, 256K x 36 ByteSafe??8Mb Sync Burst SRAMs
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производитель  GSI [GSI Technology]
домашняя страница  http://www.gsitechnology.com
Logo GSI - GSI Technology

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Rev: 1.11 9/2000
7/33
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS88118/36T-11/11.5/100/80/66
This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow
Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are
reported one clock cycle later. (See Write Parity Error Output Timing Diagram.) The Data Parity Mode (DP) pin must be tied
high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data.
Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a
parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
Write Parity Error Output Timing Diagram
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H or NC
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
ByteSafe Data Parity Control
DP
L
Check for Odd Parity
H or NC
Check for Even Parity
CK
D In A
D In B
D In C
D In D
D In E
tKQ
tLZ
DQ
QE
tKQ
tLZ
DQ
QE
D In A
D In B
D In C
D In D
D In E
Err A
Err A
Err C
Err C
tHZ
tKQX
tHZ
tKQX


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