GS816272CC-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02a 6/2006

4/29

© 2004, GSI Technology

GS816272CC-xxxV Block Diagram

A1

A0

A0

A1

D0

D1

Q1

Q0

Counter

Load

DQ

DQ

Register

Register

DQ

Register

DQ

Register

DQ

Register

DQ

Register

DQ

Register

DQ

Register

A0–An

LBO

ADV

CK

ADSC

ADSP

GW

BW

FT

G

ZZ

Power Down

Control

Memory

Array

36

36

4

A

QD

DQx1–DQx9

36

36

Note: Only x36 version shown for simplicity.

0

36

36