Philips Semiconductors

Product specification

74F1763

Intelligent DRAM controller (IDC)

1999 Jan 08

10

TIMING DIAGRAMS (Continued)

34

NOTE 1: REQ input is a don’t care during a memory refresh cycle. If REQ is asserted during a refresh cycle, it will be recognized at the first rising CP clock edge, following the refresh

cycle and its associated RAS precharge time (see Figure 4).

NOTE 2: RA0–9 and CA0–9 address inputs may be latched at anytime during a memory refresh cycle. However, a memory access cycle will not begin until after the completion of the

refresh cycle.

NOTE 3: RA0–9 and CA0–9 if in the transparent mode do not propogate to the MA0–9 outputs during a refresh cycle.

NOTE 4: MA0–9 output will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.

CP

REQ

GNT

ALE

RA0–9,

CA0–9

MA0–9

RAS

CAS

DTACK

SF01405

NOTE 1

NOTE 2

NOTE 3

NOTE 4

REFRESH

ADDR.

REFRESH

ADDR.

NEXT REFRESH ADDRESS

3-STATE

PRECHRG = 1

PRECHRG = 0

33

34

33

35

20

20

36

PRECHRG = 1

PRECHRG = 1

PRECHRG = 0

PRECHRG = 0

Figure 3. Refresh cycle timing following a memory access cycle