type apply over a junction temperature range of -5˚C to +110˚C. Unless otherwise specified, VDD = 5V, SGND = DGND =

SRCK1 = 0V. (Note 5) (Continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

I

SS3

Dynamic Output Swing Slew

Rate Control Current

(charging)

255

335

415

µA

DAC and References

VID Pins Input Logic

Low-to-High Transition

Threshold

0.63

V

VID Pins Input Logic

High-to-Low Transition

Threshold

0.315

V

DAC Accuracy Measured at

VREF Pin.

DAC codes from 0.844V to 1.708V.

-1.0

+1.0

%

DAC codes from 0.700V to 0.828V.

-1.3

+1.3

%

DAC codes from 0.844V to 1.708V.

-1.3

+1.3

%

DAC codes from 0.700V to 0.828V.

-1.5

+1.5

%

V1R7 Accuracy

17k

Ω from V1R7 to GND.

1.674

1.708

1.742

V

VSTP Offset

VSTP = 1.398V, Measured at VREF pin.

-4.5

+4.5

mV

VBOOT Offset

VBOOT = 1.00V, Measured at VREF pin.

-4.5

+4.5

mV

VSLP Offset

VSLP = 0.748V, Measured at VREF pin.

-4.5

+4.5

mV

VREF Driving Capability

source

1.5

mA

sink

11.7

mA

VDAC Driving Capability

source

1.4

mA

sink

14.3

mA

V1R7 Driving Capability

source

90

580

µA

Error Comparator

Error Comparator Input Bias

Current (Sourcing)

CMP1 = CMP2 = 1.436V.

12

21

38

µA

Error Comparator Input Offset

Voltage

CMPREF = 1.436V.

-2

+2

mV

Hysteresis Current

Rhys = 17k

Ω

82

98

115

µA

Rhys = 170k

Ω

10

µA

Error Comparator Propagation

Delay

20mV overdrive

70

ns

Current Limit

Current Limit Comparator

Input Bias Current

9

21

35

µA

Current Limit Comparator

Input Offset Voltage

ILIMREF = 1.436V.

-2

+2

mV

Current Limit Setting Current

Rhys = 17k

255

294

345

µA

Rhys = 17k

250

µA

Rhys = 170k

30

µA

Time Delays

t

BOOT

VBOOT Voltage Holdup Time From assertion of XPOK to assertion of

CLK_EN#.

10

18

30

µs

t

CPU_PWRGD

Power Good Mask For Initial

VID Voltage Settling During

Start Up

From assertion of CLK_EN# to assertion of

PGOOD.

3

5

9

ms

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