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PRINCIPLES OF OPERATION

Setting Maximum Channel Current

I

MAX +

V

IREF

R

IREF

40

(1)

Setting Dot-Correction

I

Outn +

I

MAX

DCn

127

(2)

DC15.0

105

DC15.6

111

DC14.6

104

MSB

DCOUT15

DC0.0

0

DC1.0

7

DC0.6

6

LSB

DCOUT0

DCOUT14 − DCOUT1

TLC5924

SLVS626 – JUNE 2006

maximum output current per channel can be calculated by Equation 1:

where:

power supply may be connected to the IREF pin through a resistor to change the maximum output current per

channel. The maximum output per channel is 40 times the current flowing out of the IREF pin. The maximum

current from IREF equals 1.24V/600

Ω.

The TLC5924 has the capability to fine adjust the current of each channel, OUT0 to OUT15 independently. This

is also called dot correction. This feature is used to adjust the brightness deviations of LED connected to the

output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 7-bit word. The channel

channels must be entered at the same time. Equation 2 determines the output current for each OUTn:

where:

DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127)

n = 0, 1, 2 ... 15

Dot correction data are entered for all channels at the same time. The complete dot correction data format

consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after

another. All data is clocked in with MSB first. Figure 7 shows the DC data format. The DC15.6 in Figure 7 stands

Figure 7. DC Data Format

To input data into dot correction register, MODE must be set to high. The internal input shift register is then set

to 112-bit width. After all serial data is clocked in, a high level pulse of XLAT signal connects the serial data to

the dot correction register. The dot correction registers are level-triggered latches of XLAT signal. The serial

data is latched into the dot correction registers when XLAT goes low. The data in dot correction registers is held

constant when XLAT is low. BLANK signal does not need to be high to latch in new data. Since XLAT is a

level-triggered signal when MODE is high, SCLK and SIN must not be changed while XLAT is high. (Figure 16).

8

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