поискавой системы для электроныых деталей |
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TMPR4955AF датащи(PDF) 8 Page - Toshiba Semiconductor |
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TMPR4955AF датащи(HTML) 8 Page - Toshiba Semiconductor |
8 / 168 page TMPR4955A ii 5.3.4 Example of Instruction cache locking ................................................................................... 5-6 5.4 The primary cache accessing ........................................................................................................ 5-7 5.5 Cache States .................................................................................................................................. 5-7 5.6 Cache Line Ownership .................................................................................................................. 5-8 5.7 Cache Multi-Hit Operation ........................................................................................................... 5-8 5.8 FIFO Replacement Algorithm ...................................................................................................... 5-8 5.9 Cache Testing................................................................................................................................. 5-9 5.9.1 Cache disabling ...................................................................................................................... 5-9 5.9.2 Cache Flushing....................................................................................................................... 5-9 5.10 Cache Operations ........................................................................................................................ 5-10 5.10.1 Cache Write Policy ................................................................................................................5-11 5.10.2 Data Cache Line Replacement .............................................................................................5-11 5.10.3 Instruction Cache Line Replacement.................................................................................. 5-12 5.11 Manipulation of the Caches by an External Agent ................................................................... 5-12 Chapter 6. TX4955A System Interface .................................................................................................... 6-1 6.1 Terminology ................................................................................................................................... 6-1 6.2 Explanation of System Interface of R5000 type protocol mode.................................................. 6-1 6.2.1 Interface bus........................................................................................................................... 6-2 6.2.2 Address cycle and data cycle ................................................................................................. 6-2 6.2.3 Issue cycle ............................................................................................................................... 6-3 6.2.4 Handshake signal................................................................................................................... 6-4 6.2.5 System Interface Protocol of R5000 type.............................................................................. 6-4 6.2.5.1 Master state and slave state.......................................................................................... 6-5 6.2.5.2 Shifting from the master state to the slave state ........................................................ 6-5 6.2.5.3 External arbitration....................................................................................................... 6-5 6.2.5.4 Shifting to the slave state on its own............................................................................ 6-5 6.2.6 Processor Requests and External Requests ......................................................................... 6-6 6.2.6.1 Rules relating to processor requests ............................................................................. 6-6 6.2.6.2 Processor requests.......................................................................................................... 6-7 6.2.6.3 Processor read requests ................................................................................................. 6-7 6.2.6.4 Processor write request..................................................................................................6-8 6.2.6.5 External requests ........................................................................................................... 6-8 6.2.6.6 External read requests...................................................................................................6-9 6.2.6.7 External write requests ................................................................................................. 6-9 6.2.6.8 Read responses ............................................................................................................. 6-10 6.2.7 Handling of Requests........................................................................................................... 6-10 6.2.7.1 Load miss ...................................................................................................................... 6-10 6.2.7.2 Store miss ..................................................................................................................... 6-10 6.2.7.3 Store hits........................................................................................................................6-11 6.2.7.4 Uncached load or store..................................................................................................6-11 6.2.7.5 Cache instruction operation .........................................................................................6-11 6.2.8 Processor Request and External Request Protocol ............................................................ 6-12 6.2.8.1 Processor request protocol ........................................................................................... 6-12 6.2.8.2 Processor read request protocol................................................................................... 6-12 6.2.8.3 Processor write request protocols................................................................................ 6-13 6.2.8.4 Processor single write requests ................................................................................... 6-15 6.2.8.5 Processor block write request...................................................................................... 6-17 6.2.8.6 External request protocol ............................................................................................ 6-17 6.2.8.7 External arbitration protocol....................................................................................... 6-18 6.2.8.8 External read request protocol.................................................................................... 6-19 6.2.8.9 External null request protocol..................................................................................... 6-20 6.2.8.10 External write request protocol................................................................................... 6-21 6.2.8.11 Read response protocol ................................................................................................ 6-22 6.2.9 Data Transfer ....................................................................................................................... 6-24 6.2.9.1 Data transfer pattern................................................................................................... 6-24 6.2.9.2 Independent transfer on SysAD bus ........................................................................... 6-24 6.2.10 System Interface cycle time................................................................................................. 6-25 6.2.10.1 Release latency............................................................................................................. 6-25 |
Аналогичный номер детали - TMPR4955AF |
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Аналогичное описание - TMPR4955AF |
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