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ADC08B3000 датащи(PDF) 11 Page - National Semiconductor (TI) |
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ADC08B3000 датащи(HTML) 11 Page - National Semiconductor (TI) |
11 / 32 page Converter Electrical Characteristics (Continued) NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. The following specifications apply after calibration for V A =VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P,CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f CLK = 1.5 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non- Extended Control Mode, SDR Mode, R EXT = 3300 Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface limits apply for T A =TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7) Symbol Parameter Conditions Typical (Note 8) Limits (Note 8) Units (Limits) AC ELECTRICAL CHARACTERISTICS f CLK1 Maximum Input Clock Frequency Sampling rate is 2x clock input 1.7 1.5 GHz (min) f CLK2 Minimum Input Clock Frequency Sampling rate is 2x clock input 500 MHz Input Clock Duty Cycle 500MHz ≤ Input clock frequency ≤ 1.5 GHz (Note 12) 50 20 80 % (min) % (max) t CL Input Clock Low Time (Note 11) 333 133 ps (min) t CH Input Clock High Time (Note 11) 333 133 ps (min) t RS Reset Setup Time (Note 11) 150 ps t RH Reset Hold Time (Note 11) 250 ps t RPW Reset Pulse Width (Note 11) 4 Clock Cycles (min) t LHT Differential Low to High Transition Time 10% to 90%, C L = 2.5 pF 250 ps t HLT Differential High to Low Transition Time 10% to 90%, C L = 2.5 pF 250 ps t AD Sampling (Aperture) Delay Input CLK+ Fall to Acquisition of Data 1.3 ns t AJ Aperture Jitter 0.4 ps rms t OD Input Clock to Data Output Delay (in addition to Pipeline Delay) 50% of Input Clock transition to 50% of Data transition 3.1 ns Pipeline Delay (Latency) (Note 11) Dd Outputs 13 Input Clock Cycles Db Outputs 14 Dc Outputs 13.5 Da Outputs 14.5 Over Range Recovery Time Differential V IN step from ±1.2V to 0V to get accurate conversion 1 Input Clock Cycle t WU PD low to Rated Accuracy Conversion (Wake-Up Time) 500 ns f SCLK Serial Clock Frequency (Note 11) 100 MHz t SSU Data to Serial Clock Setup Time (Note 11) 2.5 ns (min) t SH Data to Serial Clock Hold Time (Note 11) 1 ns (min) Serial Clock Low Time 4 ns (min) Serial Clock High Time 4 ns (min) t CAL Calibration Cycle Time 1.4 x 10 5 Clock Cycles t CAL_L CAL Pin Low Time See Figure 3 (Note 11) 80 Clock Cycles (min) t CAL_H CAL Pin High Time See Figure 3 (Note 11) 80 Clock Cycles (min) t CalDly Calibration delay determined by pin 127 See Section 1.1.1, Figure 3, (Note 11) 2 25 Clock Cycles (min) www.national.com 11 |
Аналогичный номер детали - ADC08B3000 |
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Аналогичное описание - ADC08B3000 |
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