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AD7765BRUZ датащи(PDF) 5 Page - Analog Devices |
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AD7765BRUZ датащи(HTML) 5 Page - Analog Devices |
5 / 21 page Preliminary Technical Data AD7765 Rev. PrC | Page 5 of 21 TIMING SPECIFICATIONS Table 2. AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, TA = +25°C, CLOAD = 25pF. Parameter Limit at TMIN, TMAX Unit Description fMCLK 500 KHz min Applied Master Clock Frequency 40 MHz max fICLK 250 kHz min Internal Modulator Clock Derived from MCLK. 20 MHz max t1 1 × tICLK typ SCO High Period t2 1 × tICLK typ SCO Low Period t3 TBD typ SCO rising edge to FSO falling edge t4 TBD typ Data Access time, FSO falling edge to data active t5 TBD ns max Initial Data Access Time, SDO active to SDO valid t6 TBD ns min SDO valid to SCO Rising Edge t7 TBD ns max SCO rising edge to SDO valid t8 TBD typ SCO rising edge to FSO rising edge t9 TBD typ FSO rising edge to SDO invalid t10 TBD × tSCO max FSO Low Period t11 TBD min FSI Low Period t121 TBD max FSI Low Period t13 TBD min SCO rising edge to SDI valid t14 TBD min SDI valid to SCO rising edge t15 TBD max SCO rising edge to SDI valid t16 TBD min FSI rising edge to SDI three-state 1 This is the max time FSI can be held low when writing to an individual (non-daisy chained) AD7764 device. |
Аналогичный номер детали - AD7765BRUZ |
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Аналогичное описание - AD7765BRUZ |
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