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AD8385ASVZ датащи(PDF) 9 Page - Analog Devices

номер детали AD8385ASVZ
подробное описание детали  10-Bit, 12-Channel Decimating LCD DECDRIVER with Level Shifters
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD8385ASVZ датащи(HTML) 9 Page - Analog Devices

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AD8385
Rev. 0 | Page 9 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVCC
DGND
SDI
SEN
SCL
BYP
TSTM
AGNDS
AGNDS
SVRL
SVRL
SVRH
VAO1
VAO2
AVCCS
NC
DIRX
DIRY
DY
CLY
CLYN
DIRXIN
DIRYIN
DYIN
CLYIN
AGND0
VID0
AVCC0,2
VID2
AGND2,4
VID4
AVCC4,6
VID6
AGND6,8
VID8
AVCC8,10
VID10
AGND10,1
VID1
AVCC1,3
VID3
AGND3,5
VID5
AVCC5,7
VID7
AGND7,9
VID9
AVCC9,11
VID11
AGND11
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17
18
20
19
21
22
23
25
24
100 99 98 97 96
91 90 89 88 87 86 85
95 94 93 92
84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PIN 1
IDENTIFIER
AD8385
TOP VIEW
(Not to Scale)
100L
14mm x 14mm
TQFP E-PAD
NC =
NO CONNECT
Figure 3. 100-Lead TQFP Package
Table 8. Pin Function Descriptions
Pin Name
Function
Description
DB(0:9)
Data Input
10-Bit Data Input. MSB = DB9.
CLK
Clock
Clock Input. Data is acquired on both edges of the CLK.
STSQ
Start Sequence
A new data loading sequence begins on the rising edge of CLK when this input was high on the
preceding rising edge of CLK.
R/L
Right/Left Select
A new data loading sequence begins on the left, with Channel 0, when this input is low; a new
data loading sequence begins on the right, with Channel 11 when this input is high.
XFR
Data Transfer
Data is transferred to the video outputs on the next rising edge of CLK when this input is high on
the rising edge of CLK.
VID0–VID11
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
V1, V2
Reference Voltages
The voltage applied between V1 and AGND sets the white video level during INV = low. The
voltage applied between V2 and AGND sets the white video level during INV = high.
VRH, VRL
Full-Scale
References
The voltage applied between these pins sets the full-scale video output voltage.
INV
Invert
When this input is high, the analog output voltages are above V2. When low, the analog outputs
voltages are below V1.
DVCC
Digital Power Supply
Digital Power Supply.
DGND
Digital Ground
This pin is normally connected to the digital ground plane.
AVCCx
Analog Power
Supplies
Analog Power Supplies.
AGNDx
Analog Ground
Analog Supply Returns.
BYP
Bypass
A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time.
SVRH, SVRL
Serial DAC Reference
Voltages
Reference Voltages for the Output Amplifiers of the Serial DACs.


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