поискавой системы для электроныых деталей |
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CAT130011LWI-GT3 датащи(PDF) 7 Page - Catalyst Semiconductor |
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CAT130011LWI-GT3 датащи(HTML) 7 Page - Catalyst Semiconductor |
7 / 14 page CAT130xx © 2007 Catalyst Semiconductor, Inc. 7 Doc. No. 1121 Rev. A Characteristics subject to change without notice Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. The serial communication protocol follows the timing shown in Figure 3. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The Ready/Busy flag can be disabled only in Ready state; no change is allowed in Busy state. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT130xx will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). The READ instruction timing is illustrated in Figure 4. For the CAT13004/08/16, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will auto- matically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Figure 3. Sychronous Data Timing Figure 4. Read Instruction Timing SK DI CS DO tDIS tPD0,tPD1 tCSMIN tCSS tDIS tDIH tSKHI tCSH VALID VALID DATA VALID tSKLOW SK CS DI DO tCSMIN STANDBY tHZ HIGH-Z HIGH-Z 11 0 AN AN-1 A0 0 DN DN-1 D1 D0 tPD0 |
Аналогичный номер детали - CAT130011LWI-GT3 |
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Аналогичное описание - CAT130011LWI-GT3 |
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