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74LCX374 Rev. 2.0.0

Logic Symbol

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, TSSOP

Pad Assignments for DQFN

(Top View)

Pin Descriptions

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Z

= High Impedance

= LOW-to-HIGH Transition

Functional Description

The LCX374 consists of eight edge-triggered flip-flops

with individual D-type inputs and 3-STATE true outputs.

The buffered clock and buffered Output Enable are com-

mon to all flip-flops. The eight flip-flops will store the state

of their individual D inputs that meet the setup and hold

time requirements on the LOW-to-HIGH Clock (CP) tran-

sition. With the Output Enable (OE) LOW, the contents of

the eight flip-flops are available at the outputs. When the

OE is HIGH, the outputs go to the high impedance state.

Operation of the OE input does not affect the state of the

flip-flops.

OE

CP

GND

CP

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

GND

CP

120

2

3

4

5

6

7

8

9

10

11

19

18

17

16

15

14

13

12

OE

Pin Names

Description

Data Inputs

CP

Clock Pulse Input

OE

Output Enable Input

3-STATE Outputs

Inputs

Outputs

CP

OE

HL

H

LL

L

XL

L

XX

HZ

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

CP

CP

OE

D

O

CP

D

O

CP

D

O

CP

D

O

CP

D

O

CP

D

O

CP

D

O

CP

D

O