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CAT24WC129KA-3TE13 датащи(PDF) 6 Page - Catalyst Semiconductor |
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CAT24WC129KA-3TE13 датащи(HTML) 6 Page - Catalyst Semiconductor |
6 / 9 page Discontinued Part CAT24WC129 6 Doc. No. 1079, Rev. V acknowledge, and internally increment the six low order address bits by one. The high order bits remain un- changed. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24WC129 in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24WC129 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issu- ing the start condition followed by the slave address for a write operation. If CAT24WC129 is still busy with the write operation, no ACK will be returned. If CAT24WC129 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the top 1/4 array of memory (locations 3000H to 3FFFH) is protected and becomes read only. The CAT24WC129 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. READ OPERATIONS The READ operation for the CAT24WC129 is initiated in the same manner as the write operation with one excep- tion, that R/ W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read The CAT24WC129’s address counter contains the ad- dress of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would ac- cess data from address N+1. If N=E (where E=16383), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24WC129 receives its slave address information (with the R/ W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a Figure 7. Page Write Timing Figure 6. Byte Write Timing A15–A8 SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS A C K * * A15–A8 SLAVE ADDRESS S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE S T A R T A7–A0 BYTE ADDRESS DATA n+63 DATA A C K S T O P A C K DATA n A C K P A C K * * *=Don't Care Bit *=Don't Care Bit |
Аналогичный номер детали - CAT24WC129KA-3TE13 |
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Аналогичное описание - CAT24WC129KA-3TE13 |
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