поискавой системы для электроныых деталей |
|
CAT25C256Y14-1.8T2 датащи(PDF) 5 Page - Catalyst Semiconductor |
|
CAT25C256Y14-1.8T2 датащи(HTML) 5 Page - Catalyst Semiconductor |
5 / 12 page 5 CAT25C128/256 Document No. 1018, Rev. I FUNCTIONAL DESCRIPTION The CAT25C128/256 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C128/256 to interface directly with many of today’s popular microcontrollers. The CAT25C128/256 contains an 8-bit instruction register. (The instruction set and the operation codes are detailed in the instruction set table) After the device is selected with CS going low, the first byte will be received. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The first byte contains one of the six op-codes that define the operation to be performed. PIN DESCRIPTION SI: Serial Input SI is the serial data input pin. This pin is used to input all opcodes, byte addresses, and data to be written to the 25C32/64. Input data is latched on the rising edge of the serial clock. SO: Serial Output SO is the serial data output pin. This pin is used to transfer data out of the CAT25C128/256. During a read cycle, data is shifted out on the falling edge of the serial clock. SCK: Serial Clock SCK is the serial clock pin. This pin is used to synchronize the communication between the microcontroller and the CAT25C128/256. Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the SCK. CS CS CS CS CS: Chip Select CS is the Chip select pin. CS low enables the CAT25C128/ 256 and CS high disables the CAT25C128/256. CS high takes the SO output pin to high impedance and forces the devices into a Standby Mode (unless an internal write operation is underway). The CAT25C128/256 draws ZERO current in the Standby mode. A high to low transition on CS is required prior to any sequence being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle. Instruction Opcode Operation WREN 0000 0110 Enable Write Operations WRDI 0000 0100 Disable Write Operations RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory INSTRUCTION SET Figure 1. Sychronous Data Timing Note: Dashed Line= mode (1, 1) — — — — VALID IN VIH VIL tCSS VIH VIL VIH VIL VOH VOL HI-Z tSU tH tWH tWL tV tCS tCSH tHO tDIS HI-Z CS SCK SI SO tRI tFI |
Аналогичный номер детали - CAT25C256Y14-1.8T2 |
|
Аналогичное описание - CAT25C256Y14-1.8T2 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |