7

ATmega128

2467OS–AVR–10/06

Port G (PG4..PG0)

Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port G output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port G pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features.

The port G pins are tri-stated when a reset condition becomes active, even if the clock is

not running.

In ATmega103 compatibility mode, these pins only serves as strobes signals to the

external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to

PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active,

even if the clock is not running. PG3 and PG4 are oscillator pins.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

19 on page 50. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally

connected to V

nected to V

AREF

AREF is the analog reference pin for the A/D Converter.

PEN

PEN is a programming enable pin for the SPI Serial Programming mode, and is inter-

nally pulled high . By holding this pin low during a Power-on Reset, the device will enter

the SPI Serial Programming mode. PEN has no function during normal operation.

Resources

A comprehensive set of development tools, application notes, and datasheets are avail-

able for download on http://www.atmel.com/avr.