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AD8328ACP-REEL датащи(PDF) 11 Page - Analog Devices |
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AD8328ACP-REEL датащи(HTML) 11 Page - Analog Devices |
11 / 20 page AD8328 Rev. A | Page 11 of 20 DATEN SDATA CLK VCC SLEEP NC GND VCC VIN– VIN+ BYP AD8328 QSOP TXEN VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SLEEP GND GND GND GND TXEN RAMP VOUT– VOUT+ GND TOKO 458PT-1087 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ DATEN SDATA CLK VIN+ VIN– 165Ω 0.1μF 0.1μF 0.1μF 10µF 0.1µF 0.1µF TO DIPLEXER ZIN = 75Ω ZIN = 150Ω Figure 20. Typical Application Circuit Table 6. Adjacent Channel Power Adjacent Channel Symbol Rate (kSym/s) Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120 160 −58 −60 −63 −66 −66 −64 320 −58 −59 −60 −64 −66 −65 640 −60 −58 −59 −61 −64 −65 1280 −62 −60 −59 −60 −61 −63 2560 −64 −62 −60 −59 −60 −61 5120 −66 −65 −62 −61 −59 −60 The output impedance of the AD8328 is 300 Ω, regardless of whether the amplifier is in transmit enable or transmit disable mode. This, when combined with a 2:1 voltage ratio (4:1 impedance ratio) transformer, eliminates the need for external back termination resistors. If the output signal is being evaluated using standard 50 Ω test equipment, a minimum loss 75 Ω to 50 Ω pad must be used to provide the test circuit with the proper impedance match. The AD8328 evaluation board provides a convenient means to implement a matching attenuator. Soldering a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω resistor in the R16 placeholder allows testing on a 50 Ω system. When using a matching attenuator, it should be noted that there is a 5.7 dB of power loss (7.5 dB voltage) through the network. POWER SUPPLY The 5 V supply should be delivered to each of the VCC pins via a low impedance power bus to ensure that each pin is at the same potential. The power bus should be decoupled to ground using a 10 μF tantalum capacitor located close to the AD8328. In addition to the 10 μF capacitor, each VCC pin should be individually decoupled to ground with ceramic chip capacitors located close to the pins. The bypass pin, BYP, should also be decoupled. The PCB should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the AD8328 and the output transformer. All AD8328 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes. SIGNAL INTEGRITY LAYOUT CONSIDERATIONS Careful attention to printed circuit board layout details will prevent problems due to board parasitics. Proper RF design techniques are mandatory. The differential input and output traces should be kept as short as possible. Keeping the traces short minimizes parasitic capacitance and inductance. This is most critical between the outputs of the AD8328 and the 2:1 output transformer. It is also critical that all differential signal paths be symmetrical in length and width. In addition, the input and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. Following these guidelines optimizes the overall performance of the AD8328 in all applications. |
Аналогичный номер детали - AD8328ACP-REEL |
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Аналогичное описание - AD8328ACP-REEL |
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