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CD3206BB датащи(PDF) 9 Page - NXP Semiconductors |
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CD3206BB датащи(HTML) 9 Page - NXP Semiconductors |
9 / 18 page Philips Semiconductors Product specification FB2031 9-bit latched/registered/pass-thru Futurebus+ transceiver 1995 May 25 9 LIVE INSERTION SPECIFICATIONS SYMBOL PARAMETER LIMITS UNIT SYMBOL PARAMETER MIN NOM MAX UNIT VBIASV Bias pin voltage VCC = 0 to 5.25V, Bn = 0 to 2.0V 4.5 5.5 V IBIASV Bias pin DC current VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 1 mA IBIASV Bias in DC current VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 10 µA VBn Bus voltage during prebias B0 – B8 = 0V, Bias V = 5.0V 1.62 2.1 V ILM Fall current during prebias B0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA IHM Rise current during prebias B0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA IBnPEAK Peak bus current during insertion VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns 10 mA IOLOFF Power up current VCC = 0 to 5.25V, OEB0 = 0.8V 100 µA IOLOFF Power u current VCC = 0 to 2.2V, OEB0 = 0 to 5V 100 µA tGR Input glitch rejection VCC = 5.0V 1.35 1.0 ns AC ELECTRICAL CHARACTERISTICS (Industrial) A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CL = 50pF, RL = 500Ω Tamb = –40 to +85°C, VCC = 5V±10%, CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency Waveform 4 120 150 100 MHz tPLH tPHL Propagation delay (thru mode) Bn to An Waveform 1, 2 2.5 2.4 4.4 4.2 5.9 5.5 2.3 2.4 7.0 6.2 ns tPLH tPHL Propagation delay (transparent latch) Bn to An Waveform 1, 2 2.9 2.8 4.6 4.3 6.2 5.9 2.7 2.5 7.1 7.0 ns tPLH tPHL Propagation delay LCBA to An Waveform 1, 2 2.6 2.4 4.1 4.7 5.5 6.1 2.0 2.0 6.2 6.8 ns tPLH tPHL Propagation delay SEL0 or SEL1 to An Waveform 1, 2 1.5 1.7 3.8 3.9 5.2 6.0 1.2 1.5 6.2 6.5 ns tPZH tPZL Output enable time from High or Low OEA to An Waveform 5, 6 2.1 2.0 3.5 3.8 4.8 5.3 1.8 1.7 6.0 6.3 ns tPHZ tPLZ Output disable time to High or Low OEA to An Waveform 5, 6 1.9 1.7 3.4 3.2 4.8 4.8 1.6 1.5 5.5 5.5 ns tTLH tTHL Output transition time, An Port 10% to 90%, 90% to 10% Test Circuit and Waveforms 3.0 1.7 7.5 4.0 ns tSK(o) Output to output skew for multiple channels1 Waveform 3 0.5 1.0 1.5 ns tSK(p) Pulse skew 2 tPHL – tPLH MAX Waveform 2 0.5 1.0 1.0 ns NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100µA, but the parts will continue to function normally. 6. B0 – B8 clamps remain active for a minimum of 80ns following a High-to-Low transition. |
Аналогичный номер детали - CD3206BB |
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Аналогичное описание - CD3206BB |
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