Philips Semiconductors

Product specification

FB2031

9-bit latched/registered/pass-thru Futurebus+ transceiver

1995 May 25

9

LIVE INSERTION SPECIFICATIONS

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

MIN

NOM

MAX

UNIT

Bias pin voltage

4.5

5.5

V

Bias pin DC current

Bias V = 4.5 to 5.5V

1

mA

Bias in DC current

Bias V = 4.5 to 5.5V

10

µA

Bus voltage during prebias

B0 – B8 = 0V, Bias V = 5.0V

1.62

2.1

V

Fall current during prebias

B0 – B8 = 2V, Bias V = 4.5 to 5.5V

1

µA

Rise current during prebias

B0 – B8 = 1V, Bias V = 4.5 to 5.5V

-1

µA

Peak bus current during

insertion

10

mA

Power up current

100

µA

Power u current

100

µA

Input glitch rejection

1.35

1.0

ns

AC ELECTRICAL CHARACTERISTICS (Industrial)

A PORT LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

UNIT

MIN

TYP

MAX

MIN

MAX

Maximum clock frequency

Waveform 4

120

150

100

MHz

Propagation delay (thru mode)

Bn to An

Waveform 1, 2

2.5

2.4

4.4

4.2

5.9

5.5

2.3

2.4

7.0

6.2

ns

Propagation delay (transparent latch)

Bn to An

Waveform 1, 2

2.9

2.8

4.6

4.3

6.2

5.9

2.7

2.5

7.1

7.0

ns

Propagation delay

LCBA to An

Waveform 1, 2

2.6

2.4

4.1

4.7

5.5

6.1

2.0

2.0

6.2

6.8

ns

Propagation delay

SEL0 or SEL1 to An

Waveform 1, 2

1.5

1.7

3.8

3.9

5.2

6.0

1.2

1.5

6.2

6.5

ns

Output enable time from High or Low

OEA to An

Waveform 5, 6

2.1

2.0

3.5

3.8

4.8

5.3

1.8

1.7

6.0

6.3

ns

Output disable time to High or Low

OEA to An

Waveform 5, 6

1.9

1.7

3.4

3.2

4.8

4.8

1.6

1.5

5.5

5.5

ns

Output transition time, An Port

10% to 90%, 90% to 10%

Test Circuit and

Waveforms

3.0

1.7

7.5

4.0

ns

Output to output skew for multiple

Waveform 3

0.5

1.0

1.5

ns

Waveform 2

0.5

1.0

1.0

ns

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any

6. B0 – B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.