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AM29PDS322DT35WMI датащи(PDF) 10 Page - Advanced Micro Devices |
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AM29PDS322DT35WMI датащи(HTML) 10 Page - Advanced Micro Devices |
10 / 51 page 8 Am29PDS322D 23569A5 December 4, 2006 D A TA SH EE T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29PDS322D Device Bus Operations Legend: L = Logic Low = V IL, H = Logic High = VIH, VID = 9.0–11.0 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, A IN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 2. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 15 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Read Mode Random Read (Non-Page Mode Read) The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the power control and should be used for device selec- tion. OE# is the output control and should be used to gate data to the output pins if the device is selected. Address access time (t ACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE) is the delay from the stable ad- dresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable for at least t ACC–tOE time). Operation CE# OE# WE# RESET# WP#/ACC Addresses (Note 1) DQ0–DQ15 Read L L H H L/H A IN D OUT Write L H L H (Note 2) A IN D IN Standby V CC ± 0.3 V X X V CC ± 0.3 V H X High-Z Output Disable L H H H L/H X High-Z Reset X X X L L/H X High-Z Sector Protect (Note 1) L H L VID L/H SA, A6 = L, A1 = H, A0 = L DIN Sector Unprotect (Note 1) L H L V ID (Note 2) SA, A6 = H, A1 = H, A0 = L D IN Temporary Sector Unprotect X X X VID (Note 2) AIN DIN |
Аналогичный номер детали - AM29PDS322DT35WMI |
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Аналогичное описание - AM29PDS322DT35WMI |
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