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74LVQ174SC датащи(PDF) 2 Page - Fairchild Semiconductor |
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74LVQ174SC датащи(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Functional Description The LVQ174 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LVQ174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Output MR CP D Q LX X L H HH H LL HL X Q |
Аналогичный номер детали - 74LVQ174SC |
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Аналогичное описание - 74LVQ174SC |
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