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74LVQ573QSC датащи(PDF) 1 Page - Fairchild Semiconductor |
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74LVQ573QSC датащи(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 2001 Fairchild Semiconductor Corporation DS011361 www.fairchildsemi.com February 1992 Revised June 2001 74LVQ573 Low Voltage Octal Latch with 3-STATE Outputs General Description The LVQ573 is a high-speed octal latch with buffered com- mon Latch Enable (LE) and buffered common Output Enable (OE) inputs. The LVQ573 is functionally identical to the LVQ373 but with inputs and outputs on opposite sides of the package. Features s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75 Ω s 4 kV minimum ESD immunity Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Pin Descriptions Connection Diagram Truth Table H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Order Number Package Number Package Description 74LVQ573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ573QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE 3-STATE Output Enable Input O0–O7 3-STATE Latch Outputs Inputs Outputs OE LE D On LH H H LH L L LL X O0 HX X Z |
Аналогичный номер детали - 74LVQ573QSC |
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Аналогичное описание - 74LVQ573QSC |
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