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LS7566R датащи(PDF) 3 Page - LSI Computer Systems |
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LS7566R датащи(HTML) 3 Page - LSI Computer Systems |
3 / 13 page CMR (x0CMR, x1CMR, x2CMR, x3CMR): The CMR is a write only register, which when written into, generates transient signals to perform load and reset operations as described below: CMR: B7 B6 B5 B4 B3 B2 B1 B0 B0 = 0: Nop = 1: Reset CNTR and sign to 0. (Should not be combinedwith load_CNTR operation). B1 = 0: Nop = 1: Load CNTR from PR. Affects all 24 bits. (Should not be combined with reset_CNTR operation) B2 = 0: Nop = 1: Load OL from CNTR. Affects all 24 bits. B3 = 0: Nop = 1: Reset STR. Affects status bits corresponding to carry, borrow, compare and index. Status bits corresponding to count_enable, count direction and sign are not affected. B4 = 0: Nop. 1: Master reset. Resets MDR0, MDR1, STR, CNTR, PR, OL, ISR and IMR B5 = 0: Nop 1: Set sign bit B6 = 0: Nop 1: Reset sign bit B7 = 0: Nop. 1: Reset ISR bit for the selected axis ISR: The ISR is a trans-axis global register used to hold the interrupt assertion status of all the axes. It is a 4-bit read-only register with the following bit assignment. ISR: B3 B2 B1 B0 B0 = 0: axis_0 interrupt cleared = 1: axis_0 interrupt asserted B1 = 0: axis_1 interrupt cleared = 1: axis_1 interrupt asserted B2 = 0: axis_2 interrupt cleared = 1: axis_2 interrupt asserted B3 = 0: axis_3 interrupt cleared = 1: axis_3 interrupt asserted An ISR bit gets set when the FLGa output of the associated axis switches low. For this reason, in order for the interrupt to be enabled for any axis, its associat- ed FLGa output must be enabled. In addition, the associated IMR bit must also be set for the interrupt to be enabled. An individual ISR bit can be cleared through its axis relevant CMR register. The ISR is cleared upon power-up. A read of ISR produces a joint read of ISR and IMR (interrupt mask register) with ISR occupying the upper nibble and IMR occupying the lower nibble of the databus. 7566R-121405-3 |
Аналогичный номер детали - LS7566R |
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Аналогичное описание - LS7566R |
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