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TDA8761M датащи(PDF) 9 Page - NXP Semiconductors

номер детали TDA8761M
подробное описание детали  9-bit analog-to-digital converter for digital video
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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1995 Mar 20
9
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for
digital video
TDA8761
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 511:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb =25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to code 511 at Tamb =25 °C.
3. Analog input voltage range can be derived from VRT − VRB difference. It is
4.
5. fi = 11 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz.
6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No
glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB
× 6.02 + 1.76 dB.
9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
11. Output data acquisition: the output data is available after the maximum delay time of td.
3-state output delay times; see Fig.4
tdZH
enable HIGH
tbf
tbf
ns
tdZL
enable LOW
tbf
tbf
ns
tdHZ
disable HIGH
tbf
tbf
ns
tdLZ
disable LOW
tbf
tbf
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
RT
V
RB
() 8
×
9
-------------------------------------------
GER
V
511
V
0
() 1.5 V
1.5 V
---------------------------------------------------
100
×
=


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