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CDCE949PWR датащи(PDF) 7 Page - Texas Instruments |
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CDCE949PWR датащи(HTML) 7 Page - Texas Instruments |
7 / 31 page www.ti.com DEVICE CHARACTERISTICS (Continued) PARAMETER MEASUREMENT INFORMATION 10pF 1kW LVCMOS CDCE949 CDCEL949 1kW LVCMOS LVCMOS CDCE949 CDCEL949 Driver Impedance ~50 W LineImpedance Zo=50 W Series Termination (Optional) CDCE949 CDCEL949 SCAS844 – JUNE 2007 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT SAVE THIS CDCEL949 – LVCMOS PARAMETER FOR VDDOUT = 1.8 V – MODE VDDOUT = 1.7 V, IOH = –0.1 mA 1.6 VOH LVCMOS high-level output voltage VDDOUT = 1.7 V, IOH = –4 mA 1.4 V VDDOUT = 1.7 V, IOH = –8 mA 1.1 VDDOUT = 1.7 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 1.7 V, IOL = 4 mA 0.3 V VDDOUT = 1.7 V, IOL = 8 mA 0.6 tPLH, Propagation delay PLL bypass 2.6 ns tPHL tr/tf Rise and fall time VDDOUT = 1.8 V (20%–80%) 0.7 ns 1 PLL switching, Y2-to-Y3 70 120 ps tjit(cc) Cycle-to-cycle jitter(2) (3) 4 PLLs switching, Y2-to-Y9 120 170 1 PLL switching, Y2-to-Y3 90 140 ps tjit(per) Peak-to-peak period jitter (2)(3) 4 PLLs switching, Y2-to-Y9 130 190 fOUT = 50 MHz; Y1-to-Y3 60 ps tsk(o) Output skew(4) fOUT = 50 MHz; Y2-to-Y5 or Y6-to-Y9 160 odc Output duty cycle(5) fVCO = 100 MHz; Pdiv = 1 45 55 % SDA/SCL PARAMETER VIK SCL and SDA input clamp voltage VDD = 1.7 V; II = –18 mA –1.2 V IIH SCL and SDA input current VI = VDD; VDD = 1.9 V ±10 μA VIH SDA/SCL input high voltage(6) 0.7 VDD V 0.3 VIL SDA/SCL input low voltage(6) V VDD 0.2 VOL SDA low-level output voltage IOL = 3 mA, VDD = 1.7 V V VDD CI SCL/SDA input capacitance VI = 0 V or VDD 3 10 pF (1) All typical values are at respective nominal VDD. (2) 10000 cycles. (3) Jitter depends on device configuration. Data is taken under the following conditions: 1-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at Y2), 4-PLL: fIN = 27 MHz, Y2/3 = 27 MHz, (measured at Y2), Y4/5 = 16.384 MHz, Y6/7 = 74.25 MHz, Y8/9 = 48 MHz. (4) The tsk(o) specification is only valid for equal loading of each bank of outputs and outputs are generated from same divider; data sampled on rising edge (tr). (5) odc depends on output rise- and fall-time (tr/tf). (6) SDA and SCL pins are 3.3-V tolerant. Figure 1. Test Load Figure 2. Test Load for 50 Ω Board Environment 7 Submit Documentation Feedback |
Аналогичный номер детали - CDCE949PWR |
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Аналогичное описание - CDCE949PWR |
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