поискавой системы для электроныых деталей |
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TDA8787AHL датащи(PDF) 9 Page - NXP Semiconductors |
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TDA8787AHL датащи(HTML) 9 Page - NXP Semiconductors |
9 / 24 page 2000 Nov 14 9 Philips Semiconductors Product specification 10-bit, 3.0 V, up to 25 Msps analog-to-digital interface for CCD cameras TDA8787A Correlated Double Sampling (CDS) (pin IN) Vi(CDS)(p-p) CDS input amplitude (video signal) (peak-to-peak value) VCC = 2.85 V 650 −− mV VCC ≥ 3.0 V 800 −− mV Vi(rst)(max) maximum CDS input reset pulse amplitude 500 −− mV Ii input current at floating gate level −1 − +1 µA Ci input capacitance − 2 − pF tCDS(min) CDS control pulses minimum active time Vi(CDS)(p-p) = 800 mV; black-to-white transition in 1 pixel ( ±2 LSB typical); Tamb =25 °C; note 1 fpix =18MHz (TDA8787AHL) 11 15 − ns fpix =25MHz (TDA8787AHL/S1) 911 − ns th(IN-SHP) hold time SHP to IN Tamb =25 °C; see Figs 3 and 4 − 12 ns th(IN-SHD) hold time SHD to IN Tamb =25 °C; see Figs 3 and 4 − 12 ns Amplifier DRPGA PGA dynamic range − 36 − dB ∆G PGA PGA gain step −0.3 − +0.3 dB Analog-to-Digital Converter (ADC) LE(i) integral non-linearity error fpix = 18 MHz; ramp input −±1.3 ±2.5 LSB LE(d) differential non-linearity error fpix = 18 MHz; ramp input −±0.5 ±0.9 LSB Total chain characteristics (CDS, PGA and ADC) fpix(max) maximum pixel frequency 25 −− MHz fpix(min) minimum pixel frequency 2 −− MHz tCLKH clock HIGH time 15 −− ns tCLKL clock LOW time 15 −− ns td(SHD-CLK) time delay SHD to CLK see Fig.3 10 −− ns tsu(BLK-CLK) set-up time of BLK compared to CLK 10 −− ns Vi(IN) video input dynamic signal for ADC full-scale output PGA input code = 0 800 −− mV PGA input code = 383 12.7 −− mV Ntot(rms) total noise from CDS input to ADC output (RMS value) see Fig.8 PGA input code = 0 − 0.15 − LSB PGA input code = 96 − 0.8 − LSB Vn(i)(eq)(rms) equivalent input noise voltage (RMS value) PGA input code = 383 − 70 −µV PGA input code = 0 − 120 −µV SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
Аналогичный номер детали - TDA8787AHL |
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Аналогичное описание - TDA8787AHL |
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