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CS5560 датащи(PDF) 6 Page - Cirrus Logic |
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CS5560 датащи(HTML) 6 Page - Cirrus Logic |
6 / 32 page CS5560 6 DS713A5 7/31/07 SWITCHING CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%; VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5% Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF. 8. CAL can be controlled by the same signal used for RST. If CAL goes high simultaneously with RST, a calibration will be performed, but CAL must remain high until RDY falls. 9. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls. 10. If CONV is held low continuously, conversions occur every 320 MCLK cycles. If RDY is tied to CONV, conversions will occur every 322 MCLKs. If CONV is operated asynchronously to MCLK, a conversion may take up to 324 MCLKs. RDY falls at the end of conversion. 11. RDY will fall when the device is fully operational when coming out of sleep mode. Parameter Symbol Min Typ Max Unit Master Clock Frequency Internal Oscillator External Clock XIN fclk 12 0.5 14 16 16 16.2 MHz MHz Master Clock Duty Cycle 40 - 60 % Reset RST Low Time tres 1- - µs RST rising to RDY falling Internal Oscillator External Clock twup - - 120 1536 - - µs MCLKs Calibration CAL pulse width (Note 8) tpw 4- - MCLKs CAL high setup time to RST rising (Note 8) tccw 0- - ns Calibration Time RST rising (CAL high) to RDY falling tscl - 331458 - MCLKs Calibration Time CAL rising (RST high) to RDY falling tcal - 331458 - MCLKs Conversion CONV Pulse Width tcpw 4- - MCLKs BP/UP setup to CONV falling (Note 9) tscn 0- - ns CONV low to start of conversion tscn -- 2 MCLKs Perform Single Conversion (CONV high before RDY falling) tbus 20 - - MCLKs Conversion Time (Note 10) Start of Conversion to RDY falling tbuh -- 324 MCLKs Sleep Mode SLEEP low to low-power state SLEEP high to device active (Note 11) tcon tcon - - 50 3083 - - µs MCLKs |
Аналогичный номер детали - CS5560 |
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Аналогичное описание - CS5560 |
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