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SN74LV161284DLG4 датащи(PDF) 1 Page - Texas Instruments

номер детали SN74LV161284DLG4
подробное описание детали  19-BIT BUS INTERFACE
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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SN74LV161284DLG4 датащи(HTML) 1 Page - Texas Instruments

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SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D 4.5-V to 5.5-V VCC Operation
D 1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
D Designed for IEEE Std 1284-I (Level-1 Type)
and IEEE Std 1284-II (Level-2 Type)
Electrical Specifications
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 250 mA Per
JEDEC 17
D ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 300-V Machine Model (A115-A)
– 2000-V Charged-Device Model (C101)
description/ordering information
The SN74LV161284 is designed for 4.5-V to
5.5-V VCC operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
This device has eight bidirectional bits; data can
flow in the A-to-B direction when DIR is high, and
in the B-to-A direction when DIR is low. This
device also has five drivers, which drive the cable
side, and four receivers. The SN74LV161284 has
one receiver dedicated to the HOST LOGIC line
and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and
PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low.
This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II
(level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT,
all cable-side pins have a 1.4-k
Ω integrated pullup resistor. The pullup resistor is switched off if the associated
output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off,
PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the
output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP
DL
Tube
SN74LV161284DL
LV161284
–40
°C to 85°C
SSOP – DL
Tape and reel
SN74LV161284DLR
LV161284
TSSOP – DGG
Tape and reel
SN74LV161284DGGR
LV161284
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
(TOP VIEW)
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HD
A9
A10
A11
A12
A13
VCC
A1
A2
GND
A3
A4
A5
A6
GND
A7
A8
VCC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
DIR
Y9
Y10
Y11
Y12
Y13
VCC CABLE
B1
B2
GND
B3
B4
B5
B6
GND
B7
B8
VCC CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN


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