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CX20470 датащи(PDF) 8 Page - Skyworks Solutions Inc.

номер детали CX20470
подробное описание детали  CDMA Baseband Analog Processor
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производитель  SKYWORKS [Skyworks Solutions Inc.]
домашняя страница  http://www.skyworksinc.com
Logo SKYWORKS - Skyworks Solutions Inc.

CX20470 датащи(HTML) 8 Page - Skyworks Solutions Inc.

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CX20470
CDMA BAP
8
Skyworks – Preliminary
101106A
Proprietary Information and Specifications are Subject to Change
August 24, 2000
Table 1. CX20470 BAP Signal Description: 100-Pin
µµµµBGA Package (2 of 4)
Pin #
Name
I/O Type
Description
Receive Signal Path (continued)
F9
TXD5 or TXIIN/
D,I or A,I
Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 5) for
digital TX data input, or TX I channel analog differential input (–) for MSM3100 interface
mode.
G8
TXD4 or TXQIN
D,I or A,I
Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 4) for
digital TX data input or TX Q channel analog differential input (+) for MSM3100 interface
mode.
H9
TXD3 or TXQIN/
D,I or A,I
Configurable pin. Can be configured to be transmit digital 8-bit data from MSM (bit 3) for
digital TX data input or TX Q channel analog differential input (–) for MSM3100 interface
mode.
G9
TXD2
D,I,Z
Transmit digital 8-bit data from MSM (bit 2)
H10
TXD1
D,I,Z
Transmit digital 8-bit data from MSM (bit 1)
J10
TXD0
D,I,Z
Transmit digital 8-bit data from MSM (bit 0)
B9
TXCLK/ or CHIPx8IN
D,I,Z
Configurable pin. Can be configured to be negative differential transmit clock input or
CHIPx8 clock input.
H7
TXI
A,O,Z
Baseband transmit in-phase analog differential output.
K7
TXI/
A,O,Z
Baseband transmit in-phase analog differential output.
J7
TxQ
A,O,Z
Baseband transmit quadrature analog differential output (+).
K6
TxQ/
A,O,Z
Baseband transmit quadrature analog differential output (–).
G7
FM_MOD
A,O,S
FM modulation analog output signal.
Dual VHF and Clock Synthesizers
F4
RXPLLIN
A,I,Z
Receive synthesizer divider differential input (+).
E3
RXPLLIN/
A,I,Z
Receive synthesizer divider differential input (–).
E2
RXPDOUT
A,O,Z
Receiver synthesizer (RX PLL) phase detector charge pump output.
H6
PLLFILTR
A,O,Z
Loop filter for clock PLL when enabled.
F2
TXPDOUT
A,O
Transmit synthesizer (TX PLL) phase detector charge pump output.
G2
TXPLLIN
A,I,Z
Transmit synthesizer divider differential input (
+) from the external VCO buffer.
G4
TXPLLIN/
A,I,Z
Transmit synthesizer divider differential input (
) from the external VCO buffer.
J8
SYNPRES
D,I,Z
When high, disables the synthesizers.
J2
SYNENA
D,I,Z
Synthesizer three-wire serial interface enable.
K2
SYNDATA
D,I,Z
Synthesizer three-wire serial interface data input.
K3
SYNCLK
D,I,Z
Synthesizer three-wire serial interface clock input.
K1
LOCK
A,O,L
Lock detect indicator for the receive and transmit VHF synthesizers.
Mode Control
J9
FM/
D,I,Z
FM or CDMA mode select input.
J3
SLEEP/
D,I,Z
CDMA sleep mode is enabled when this input pin is low and FM/ is high.
J4
IDLE/
D,I,Z
CDMA idle or FM idle modes are enabled when this input is low and SLEEP/ is high.
F7
PDBTCXO
D,I,Z
When this signal is activated, the BAP will power-down its TCXO buffer input clock.
H4
TEST/ or SPKR2O
D,I or A,O
Configurable pin. Can be configured to be test purposes control pin or single-ended
speaker output
System Clock and Synthesized Clock
K9
TCXO
A,I,Z
TCXO 19.2/19.68/19.8 MHz clock input.
A10
CHIPx8
D,O,L
9.8304 MHz digital clock output.
K10
TCXO/4
D,O,L
This signal, typically 4.92 MHz, is digitally synthesized from the TCXO input clock.


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