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SI5368 датащи(PDF) 1 Page - Silicon Laboratories |
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SI5368 датащи(HTML) 1 Page - Silicon Laboratories |
1 / 18 page Preliminary Rev. 0.3 3/07 Copyright © 2007 by Silicon Laboratories Si5368 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5368 ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Description The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The Si5368 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5368 is based on Silicon Laboratories' 3rd- generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5368 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Wireless basestations Data converter clocking xDSL SONET/SDH + PDH clock synthesis Test and measurement Features Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs w/jitter generation as low as 0.3 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (60Hz to 8.4kHz) Meets OC-192 GR-253-CORE jitter specifications Four clock inputs w/manual or automatically controlled hitless switching Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) SONET frame sync switching and regeneration Support for ITU G.709 and custom FEC ratios (255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputs Digitally-controlled output phase adjust I2C or SPI programmable settings On-chip voltage regulator for 1.8 or 2.5 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant PRELIMINARY DATA SHEET Rate Select I2C/SPI Port Clock Select Xtal or Refclock CKOUT2 CKIN1 CKOUT1 CKIN2 Control ÷ NC1 ÷ NC2 Latency Control CKIN3 CKIN4 CKOUT4 ÷ NC4 CKOUT5/FS_OUT Input Clock 3 Input Clock 4 Output Clock 2 ÷ NFS VDD (1.8 or 2.5 V) GND ÷ N32 ÷ N31 DSPLL ® ÷ N2 CKOUT3 ÷ NC3 ÷ N33 ÷ N34 Device Interrupt LOL/LOS/FOS Alarms FSYNC Realignment |
Аналогичный номер детали - SI5368 |
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Аналогичное описание - SI5368 |
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