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74AUP2G07GF датащи(PDF) 10 Page - NXP Semiconductors |
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74AUP2G07GF датащи(HTML) 10 Page - NXP Semiconductors |
10 / 16 page 74AUP2G07_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 12 June 2007 10 of 16 NXP Semiconductors 74AUP2G07 Low-power dual buffer with open-drain output [1] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, set-up and hold times and pulse width RL =1MΩ. Table 9. Measurement points Supply voltage Input Output VCC VM VM VX 0.8 V to 1.6 V 0.5 × V CC 0.5 × V CC VOL + 0.1 V 1.65 V to 2.7 V 0.5 × VCC 0.5 × V CC VOL + 0.15 V 3.0 V to 3.6 V 0.5 × VCC 0.5 × V CC VOL + 0.3 V Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times 001aac521 PULSE GENERATOR DUT RT VI VO VEXT VCC RL 5 k Ω CL Table 10. Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V VCC ≤ 3 ns 5 pF, 10 pF, 15 pF and 30 pF 5 k Ω or 1 MΩ open GND 2 × VCC |
Аналогичный номер детали - 74AUP2G07GF |
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Аналогичное описание - 74AUP2G07GF |
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