поискавой системы для электроныых деталей |
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FM3808DK датащи(PDF) 11 Page - Ramtron International Corporation |
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FM3808DK датащи(HTML) 11 Page - Ramtron International Corporation |
11 / 27 page N O T R EC O M M EN D ED FO R N EW D ES IG N S La st Ti m e B uy : S ept . 200 6 N o Di re ct Re pl ac em en t Al te rn at e So lu tio n: FM 18 08 +F M 40 05 FM3808 Rev. 1.3 (EOL) Feb. 2006 Page 11 of 27 Watchdog Timer The Watchdog timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running (/OSCEN=0) for the watchdog to function. It begins counting down from the value loaded in the Watchdog Timer register (7FF7h). The counter consists of a loadable register and a free running counter. On power up, the watchdog timeout value in 7FF7h is loaded into the counter load register. Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe WDS bit (7FF7h bit D7) is set to 1. The counter is compared to terminal value of 0. If the counter reaches this value, it causes an internal flag and an optional interrupt output (see interrupts below). The user can prevent the timeout interrupt by setting WDS bit to 1 prior to the counter reaching 0. This causes the counter to be reloaded with the watchdog timeout value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and flag never occurs. New timeout values can be written by setting the watchdog write bit (7FF7h bit D6) to 0. When the /WDW bit is 0 (from a previous operation), new writes to the watchdog timeout value 7FF7h bits D5- D0 allow the timeout value to be modified. When /WDW is a 1, then writes to bits 7FF7h bits D4-D0 will be ignored. The /WDW function allows a user to set the WDS bit without concern that the watchdog timer value will be modified. A logical diagram of the watchdog timer is shown below. Note that setting the watchdog timeout value to 0 would be otherwise meaningless and therefore disables the watchdog function. The output of the watchdog timer is a flag bit WDF (7FF0h bit D7) that is set if the watchdog is allowed to timeout. The flag is set upon a watchdog timeout and cleared when the Flags/Control register is read by the user. The user can also enable an optional interrupt source to drive the INT pin if the watchdog timeout occurs. The interrupt function is described on page 13. Oscillator Clock Divider Counter Watchdog register 32.768 kHz 1 Hz 32 Hz WDS WDW 7FF7.5-0 Zero Compare WDF 7FF0.7 Load Register Q Q D write to Watchdog register Figure 3. Watchdog Timer Block Diagram |
Аналогичный номер детали - FM3808DK |
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Аналогичное описание - FM3808DK |
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