поискавой системы для электроныых деталей |
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TLC5615IDR датащи(PDF) 2 Page - Texas Instruments |
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TLC5615IDR датащи(HTML) 2 Page - Texas Instruments |
2 / 21 page www.ti.com _ + DAC 10-Bit DAC Register Power-ON Reset Control Logic 16-Bit Shift Register 4 Dummy Bits 2 0s 10 Data Bits (LSB) (MSB) REFIN AGND CS SCLK DIN OUT (Voltage Output) _ + DOUT R R 2 PACKAGE/ORDERING INFORMATION TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. DIN 1 I Serial data input SCLK 2 I Serial clock input CS 3 I Chip select, active low DOUT 4 O Serial data output for daisy chaining AGND 5 Analog ground REFIN 6 I Reference input OUT 7 O DAC analog voltage output VDD 8 Positive power supply For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 Submit Documentation Feedback |
Аналогичный номер детали - TLC5615IDR |
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Аналогичное описание - TLC5615IDR |
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