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TPS51220RHBT датащи(PDF) 8 Page - Texas Instruments |
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TPS51220RHBT датащи(HTML) 8 Page - Texas Instruments |
8 / 37 page www.ti.com TPS51220 SLVS785 – OCTOBER 2007 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. Control architecture and OVP function Selection Pin. GND: Current mode, OVP enable FUNC 11 I VREF2: D-CAP mode, OVP disable VREG3: D-CAP mode, OVP enable VREG5: Current mode, OVP disable VREF2 13 O 2V Reference Output. Bypass to (signal) GND by 0.22 μF ceramic capacitor. Overcurrent trip level and discharge mode selection pin. GND: V(OCL-ULV) , Discharge on TRIP 14 I VREF2: V(OCL-ULV), Discharge off VREG3: V(OCL-LV), Discharge off VREG5: V(OCL-LV), Discharge on VREF2 and VREG5 Linear Regulators Enable Pin. When turning on, apply greater than 1.2V and less than EN 12 I 6V. Connect to GND to Disable. VBST1 31 Supply inputs for high-side NFET driver (boot strap Terminal). Connect a capacitor (0.1 μF or greater is I recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this pin is an VBST2 26 optional. DRVL1 30 O Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7Ω, GND referenced driver. DRVL2 27 V5SW 2 I VREG5 switchover power supply input pin. 5V, 100mA Low Dropout Linear Regulator Output. Bypass to (power) GND using a 10 μF ceramic capacitor. VREG5 29 O Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW when 4.8V or above is provided. VIN 23 I Supply Input for 5V and 3.3V Linear Regulator. Typically connected to VBAT. GND 28 -- Ground 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s) :TPS51220 |
Аналогичный номер детали - TPS51220RHBT |
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Аналогичное описание - TPS51220RHBT |
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