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AD844BQ датащи(PDF) 10 Page - Analog Devices |
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AD844BQ датащи(HTML) 10 Page - Analog Devices |
10 / 16 page REV. D AD844 –10– Input Impedance At low frequencies, negative feedback keeps the resistance at the inverting input close to zero. As the frequency increases, the impedance looking into this input will increase from near zero to the open loop input resistance, due to bandwidth limitations, making the input seem inductive. If it is desired to keep the input impedance flatter, a series RC network can be inserted across the input. The resistor is chosen so that the parallel sum of it and R2 equals the desired termination resistance. The capacitance is set so that the pole determined by this RC network is about half the bandwidth of the op amp. This network is not important if the input resistor is much larger than the termina- tion used, or if frequencies are relatively low. In some cases, the small peaking that occurs without the network can be of use in extending the –3 dB bandwidth. Driving Large Capacitive Loads Capacitive drive capability is 100 pF without an external net- work. With the addition of the network shown in Figure 7, the capacitive drive can be extended to over 10,000 pF, limited by internal power dissipation. With capacitive loads, the output speed becomes a function of the overdriven output current limit. Since this is roughly ±100 mA, under these conditions, the maximum slew rate into a 1000 pF load is ± 100 V/µs. Figure 8 shows the transient response of an inverting amplifier (R1 = R2 = 1 k Ω) using the feed forward network shown in Figure 7, driving a load of 1000 pF. AD844 VOUT CL 750 22pF Figure 7. Feed Forward Network for Large Capacitive Loads Figure 8. Driving 1000 pF CL with Feed Forward Network of Figure 7 Settling Time Settling time is measured with the circuit of Figure 9. This circuit employs a false summing node, clamped by the two Schottky diodes, to create the error signal and limit the input signal to the oscilloscope. For measuring settling time, the ratio of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 k Ω, and RL = 500 Ω. For the gain of –10, R5 = 50 Ω, R6 = 500 Ω and RL was not used since the summing network loads the output with approximately 275 Ω. Using this network in a unity-gain configuration, settling time is 100 ns to 0.1% for a –5 V to +5 V step with CL = 10 pF. R5 D1 D2 R1 R2 R3 RL R6 VIN CL VOUT TO SCOPE (TEK 7A11 FET PROBE) D1, D2 IN6263 OR EQUIV. SCHOTTKY DIODE AD844 Figure 9. Settling Time Test Fixture DC Error Calculation Figure 10 shows a model of the dc error and noise sources for the AD844. The inverting input bias current, IBN, flows in the feedback resistor. IBP, the noninverting input bias current, flows in the resistance at Pin 3 (RP), and the resulting voltage (plus any offset voltage) will appear at the inverting input. The total error, VO, at the output is: V O = ( IBP RP + VOS + IBN RIN )1 + R1 R2 + I BN R1 Since IBN and IBP are unrelated both in sign and magnitude, inserting a resistor in series with the noninverting input will not necessarily reduce dc error and may actually increase it. ~ R2 VN + INN INP RP R1 IBP IBN VOS AD844 RIN Figure 10. Offset Voltage and Noise Model for the AD844 |
Аналогичный номер детали - AD844BQ |
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Аналогичное описание - AD844BQ |
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