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DEVICE INFORMATION

1

2

3

4

8

7

6

5

UGATE

BOOT

PWM

GND

PHASE

EN/PG

VDD

LGATE

5

3

7

6

8

1

2

BOOT

PWM

VDD

EN/PG

LG A T E

GND

U G A T E

PHASE

4

Exposed

Thermal

Die Pad

6

13K

2

VDD

EN /PG

BOOT

UGATE

PHASE

LGATE

GND

7

1

8

5

4

VDD

27K

3 −STATE

INPUT

CIRCUIT

PWM

3

SHOOT

−

THROUGH

PROTECTION

THERMAL

SD

TIME

UVLO

TPS28226

SLUS791 – OCTOBER 2007

SOIC-8 Package (top view)

DRB-8 Package (top view)

FUNCTIONAL BLOCK DIAGRAM

A.

For the TPS28226DRB device the thermal PAD on the bottom side of package must be soldered and connected to

the GND pin and to the GND plane of the PCB in the shortest possible way. See Recommended Land Pattern in the

Application section.

8

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Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): TPS28226