CXK77K36R320GB

Preliminary

32Mb LW R-R, rev 0.6

8 / 22

March 16, 2004

2. These parameters are guaranteed by design through extensive corner-lot characterization.

3. These parameters are measured at

± 50mV from steady state voltage.

Parameter

Symbol

-3

-33

-4

Units

Notes

Min

Max

Min

Max

Min

Max

Input Cycle Time

3.0

---

3.3

---

4.0

---

ns

Input Clock High Pulse Width

1.2

---

1.3

---

1.5

---

ns

Input Clock Low Pulse Width

1.2

---

1.3

---

1.5

---

ns

Address Input Setup Time

0.3

---

0.3

---

0.3

---

ns

1

Address Input Hold Time

0.5

---

0.6

---

0.7

---

ns

Write Enable Input Setup Time

0.3

---

0.3

---

0.3

---

ns

1

Write Enable Input Hold Time

0.5

---

0.6

---

0.7

---

ns

Sync Select Input Setup Time

0.3

---

0.3

---

0.3

---

ns

1

Sync Select Input Hold Time

0.5

---

0.6

---

0.7

---

ns

Data Input Setup Time

0.3

---

0.3

---

0.3

---

ns

1

Data Input Hold Time

0.5

---

0.6

---

0.7

---

ns

Input Clock High to Output Data Valid

---

1.6

---

1.6

---

2.0

ns

Input Clock High to Output Data Hold

0.65

---

0.65

---

0.65

---

ns

2

Input Clock High to Output Data Low-Z

0.65

---

0.65

---

0.65

---

ns

2,3

Input Clock High to Output Data High-Z

0.65

1.8

0.65

1.8

0.65

2.2

ns

2,3

Output Enable Low to Output Data Valid

---

2.5

---

2.5

---

2.5

ns

Output Enable Low to Output Data Low-Z

0.3

---

0.3

---

0.3

---

ns

2,3

Output Enable High to Output Data High-Z

---

2.5

---

2.5

---

2.5

ns

2,3

Sleep Mode Enable Time

---

15

---

15

---

15

ns

2

Sleep Mode Recovery Time

20

---

20

---

20

---

ns

2