поискавой системы для электроныых деталей |
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TMPR4937XBG-300 датащи(PDF) 7 Page - Toshiba Semiconductor |
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TMPR4937XBG-300 датащи(HTML) 7 Page - Toshiba Semiconductor |
7 / 552 page Table of Contents iii 8.4.8 DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn) .................................... 8-37 8.4.9 DMA Count Register (DM0CNTRn, DM1CNTRn).......................................................................... 8-38 8.4.10 DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) ........................................................ 8-39 8.5 Timing Diagrams ......................................................................................................................................... 8-40 8.5.1 Single Address Single Transfer from Memory to I/O (32-bit ROM) ................................................. 8-40 8.5.2 Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-41 8.5.3 Single Address Single Transfer from I/O to Memory (32-bit SRAM)............................................... 8-42 8.5.4 Single Address Burst Transfer from Memory to I/O (32-bit ROM) .................................................. 8-43 8.5.5 Single Address Burst Transfer from I/O to Memory (32-bit SRAM) ................................................ 8-44 8.5.6 Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-46 8.5.7 Single Address Single Transfer from I/O to Memory (16-bit SRAM)............................................... 8-47 8.5.8 Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) .............................. 8-48 8.5.9 Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) ............................ 8-49 8.5.10 Single Address Single Transfer from Memory to I/O (64-bit SRAM)............................................... 8-50 8.5.11 Single Address Single Transfer from I/O to Memory (64-bit SDRAM) ............................................ 8-51 8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE* Signal is Set to Output ...................................................................................... 8-52 8.5.13 Single Address Single Transfer from Memory to I/O (32-bit SDRAM) ............................................ 8-53 8.5.14 Single Address Single Transfer from I/O to Memory (32-bit SDRAM) ............................................ 8-54 8.5.15 External I/O Device – SRAM Dual Address Transfer ....................................................................... 8-55 8.5.16 External I/O Device – SDRAM Dual Address Transfer .................................................................... 8-57 8.5.17 External I/O Device (Non-burst) – SDRAM Dual Address Transfer................................................. 8-59 9. SDRAM Controller................................................................................................................................................. 9-1 9.1 Characteristics................................................................................................................................................ 9-1 9.2 Block Diagram ............................................................................................................................................... 9-2 9.3 Detailed Explanation...................................................................................................................................... 9-3 9.3.1 Supported SDRAM configurations...................................................................................................... 9-3 9.3.2 Address Mapping................................................................................................................................. 9-4 9.3.3 Initialization of SDRAM ..................................................................................................................... 9-9 9.3.4 Initialization of Memory Data, ECC/Parity .......................................................................................9-10 9.3.5 Low Power Consumption Function ................................................................................................... 9-11 9.3.6 Bus Errors .......................................................................................................................................... 9-12 9.3.7 Memory Read and Memory Write ..................................................................................................... 9-12 9.3.8 Slow Write Burst................................................................................................................................ 9-12 9.3.9 Clock Feedback ................................................................................................................................. 9-12 9.3.10 ECC ................................................................................................................................................... 9-13 9.4 Registers....................................................................................................................................................... 9-17 9.4.1 SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0) 0x8008 (ch. 1) 0x8010 (ch. 2) 0x8018 (ch. 3) .................................................................................................................................... 9-18 9.4.2 SDRAM Timing Register (SDCTR) 0x8040 ..................................................................................... 9-20 9.4.3 SDRAM Command Register (SDCCMD) 0x8058 ............................................................................ 9-22 9.4.4 ECC Control Register (ECCCR) 0xA000.......................................................................................... 9-23 9.4.5 ECC Status Register (ECCSR) 0xA008............................................................................................. 9-25 9.5 Timing Diagrams ......................................................................................................................................... 9-26 9.5.1 Single Read (64-bit Bus).................................................................................................................... 9-26 9.5.2 Single Write (64-bit Bus) ................................................................................................................... 9-28 9.5.3 Burst Read (64-bit Bus) ..................................................................................................................... 9-30 9.5.4 Burst Write (64-bit Bus) .................................................................................................................... 9-31 9.5.5 Burst Write (64-bit Bus, Slow Write Burst) ....................................................................................... 9-32 9.5.6 Single Read (32-bit Bus).................................................................................................................... 9-33 9.5.7 Single Write (32-bit Bus) ................................................................................................................... 9-35 9.5.8 Low Power Consumption and Power Down Mode ........................................................................... 9-37 9.6 SDRAM Usage Example ............................................................................................................................. 9-42 10. PCI Controller....................................................................................................................................................... 10-1 10.1 Features ........................................................................................................................................................ 10-1 10.1.1 Overall ............................................................................................................................................... 10-1 |
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Аналогичное описание - TMPR4937XBG-300 |
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