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BUF01900AIDRCRG4 датащи(PDF) 9 Page - Texas Instruments

номер детали BUF01900AIDRCRG4
подробное описание детали  Programmable Voltage Source with Memory
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

BUF01900AIDRCRG4 датащи(HTML) 9 Page - Texas Instruments

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BUF01900
BUF01901
SBOS337A − OCTOBER 2006 − REVISED OCTOBER 2006
www.ti.com
9
POWER-SUPPLY VOLTAGE
The BUF0190x can be powered using an analog supply
voltage from 7V to 18V, and a digital supply from 2V to
5.5V. The digital supply must be applied prior to the analog
supply to avoid excessive current and power consumption.
During programming of the OTP, the analog power supply
must be at least 8.5V.
BUFFER INPUT AND OUTPUT RANGE
The integrated buffer has a single p-channel input stage.
The input range includes the positive supply and extends
down to typically 0.8V above the negative supply (GND).
In a typical LCD application, this is normally sufficient be-
cause the nominal VCOM level is often close to V2/2 and,
therefore, fairly far away from either supply rail. In addition,
the adjustment range is usually not much larger than 1V in
either direction of the nominal VCOM voltage. In applica-
tions requiring a wider output swing, the output voltage to
the buffer should be limited to approximately 0.8V above
the negative power supply to keep the buffer input stage
in its linear operating region. For lower input voltages, the
output results might not be valid; however, they will also
not lead to damage of the device.
The Rail-to-Rail output stage is designed to drive large
peak currents greater than 100mA.
TWO-WIRE BUS OVERVIEW
The BUF0190x communicates through an industry-stan-
dard, two-wire interface to receive data in slave mode. This
standard uses a two-wire, open-drain interface that sup-
ports multiple devices on a single bus. Bus lines are driven
to a logic low level only. The device that initiates the com-
munication is called a master, and the devices controlled
by the master are slaves. The master generates the serial
clock on the clock signal line (SCL), controls the bus ac-
cess, and generates START and STOP conditions.
To address a specific device, the master initiates a START
condition by pulling the data signal line (SDA) from a HIGH
to LOW logic level while SCL is HIGH. All slaves on the bus
shift in the slave address byte, with the last bit indicating
whether a read or write operation is intended. During the
ninth clock pulse, the slave being addressed responds to
the master by generating an Acknowledge and pulling
SDA LOW.
Data transfer is then initiated and eight bits of data are
sent, followed by an Acknowledge bit. During data trans-
fer, SDA must remain stable while SCL is HIGH. Any
change in SDA while SCL is HIGH will be interpreted as a
START or STOP condition.
Once all data has been transferred, the master generates
a STOP condition, indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
The BUF0190x can act only as a slave device; therefore,
it never drives SCL. The SCL is only an input for the
BUF0190x.
ADDRESSING THE BUF01900 AND
BUF01901
The address of the BUF0190x in the TSSOP-8 package
is 111011x, where x is the state of the A0 pin. When the
A0 pin is LOW, the device acknowledges on address 76h.
If the A0 pin is HIGH, the device acknowledges on address
77h. Table 1 summarizes device addresses.
Table 1. Quick-Reference Table of Addresses
DEVICE/COMPONENT
ADDRESS
TSSOP Package:
A0 pin is LOW
(device will acknowledge on address 76h)
1110110
A0 pin is HIGH
(device will acknowledge on address 77h)
1110111
DFN Package:
A0 pin is LOW, A1 is LOW
(device will acknowledge on address 74h)
1110100
A0 pin is HIGH, A1 is LOW
(device will acknowledge on address 75h)
1110101
A0 pin is LOW, A1 is HIGH
(device will acknowledge on address 76h)
1110110
A0 pin is HIGH, A1 is HIGH
(device will acknowledge on address 77h)
1110111
The address of the BUF0190x in the DFN-10 package is
11101yx, where x is the state of the A0 pin and y is the state
of the A1 pin. When the A0 and A1 pins are both LOW, the
device acknowledges on address 74h. If the A0 is HIGH
and A1 is LOW, the device acknowledges on address 75h.
When the A0 is LOW, and A1 is HIGH, the device acknowl-
edges on address 76h. If the A0 and A1 pins are both
HIGH, the device address is 77h.
Other addresses are possible through a simple mask
change. Contact your TI representative for ordering infor-
mation and availability.


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