Si3460

Preliminary Rev. 0.4

9

4.1. PSE Timing Characteristics

When implemented in accordance with the recommended external components and layout guidelines, the Si3460

controller enables the following typical performance characteristics in single-port PSE applications. Refer to the

Si3460-EVB applications note, schematics, and user's guide for more details.

4.1.1. PSE Timing Diagrams

The basic sequence of applying power is shown in Figure 3. Following is the description of the function that must

be performed in each phase.

Figure 3. Detection, Classification, Powerup, and Disconnect Sequence

Table 6. PSE Timing*

Description

Symbol

Test Conditions

Min

Typ

Max

Unit

Endpoint detection delay

cycle

Time from PD connection to port to

completion of detection process.

70

400

ms

Detection time

Time required to measure PD sig-

nature resistance.

70

ms

Classification delay cycle

Time from successful detect mode

to classification complete.

10

50

ms

Classification time

10

50

ms

Power-up turn-on delay

Time from when a valid detection is

applied

30

ms

Midspan detect backoff time

2s

Current limit time

60

ms

Disconnect delay

350

ms

Time

(msec)

2.8 V

10 V

15.5 V

44 V

57 V

20.5 V