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SL23EP09ZI-1 датащи(PDF) 3 Page - SpectraLinear Inc |
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SL23EP09ZI-1 датащи(HTML) 3 Page - SpectraLinear Inc |
3 / 13 page Rev 1.1, February 2, 2007 Page 3 of 13 SL23EP09 General Description The SL23EP09 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to CLKOUT that is used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). Input and output Frequency Range The input and output frequency range is the same. But, it depends on VDD and drive levels as given in the below Table 1. VDD(V) Drive Min(MHz) Max(MHz) 3.3 HIGH 10 220 3.3 STD 10 167 2.5 HIGH 10 200 2.5 STD 10 133 Table 1. Input/Output Frequency Range If the input clock frequency is DC (GND to VDD), this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 A supply current. SpreadThru ™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP09 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency Select Input Control The SL23EP09 provides two (2) input select control pins called S1 and S2. This feature enables users to selects various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k weak pull-up resistors to VDD. PLL Bypass Mode If the S2 and S1 pins are logic High(1) and Low(0) respectively, the on-chip PLL is shutdown and bypassed, and all the nine output clocks bank A, bank B and CLKOUT clocks are driven directly from the reference input clock. In this operation mode SL23EP09 works like a non-ZDB fanout buffer. High and Low-Drive Product Options The SL23EP09 is offered with High-Drive “-1H” and Standard-Drive “-1” options. These drive options enable the users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. Skew and Zero Delay All outputs should drive the similar load to achieve output-to- output skew and input-to-output specifications given in the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading of CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL. Power Supply Range (VDD) The SL23EP09 is designed to operate in a wide power supply range from 2.3V (Min) to 3.6V (Max). An internal on- chip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Contact SLI for 1.8V power supply version ZDB called SL23EPL09. |
Аналогичный номер детали - SL23EP09ZI-1 |
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Аналогичное описание - SL23EP09ZI-1 |
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