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ADC12040CIVYX датащи(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали ADC12040CIVYX
подробное описание детали  12-Bit, 40 MSPS, 340mW A/D Converter with Internal Sample-and-Hold
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12040CIVYX датащи(HTML) 8 Page - National Semiconductor (TI)

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AC Electrical Characteristics (Continued)
Note 14: IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 xf0 +C1 xf1 +....C11 xf11) where VDR is the output driver power supply
voltage, Cn is total capacitance on the output pin, and fn is the average frequency at which that pin is toggling.
Note 15: Excludes IDR. See note 14.
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conver-
sion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
COMMON MODE VOLTAGE (V
CM)
is the d.c. potential
present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time during one cycle that a
repetitive digital waveform is high to the total time of one
period. The specification here refers to the ADC clock input
signal.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It is the difference between the Positive
Full Scale Error and the Negative Full Scale Error:
Gain Error = Pos. Full Scale Error − Neg. Full Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (12 LSB below the first code transition)
through positive full scale (12 LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC12040 is guaranteed
not to have any missing codes.
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of 12 LSB
above negative full scale (−V
REF).
OFFSET ERROR is the difference between the two input
voltages [ (V
IN+) – (VIN−) ] required to cause a transition
from code 2047 to 2048.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
sented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 112 LSB
below the reference voltage.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC12040, PSRR1 is the ratio of the
change in Full-Scale Error that results from a change in the
d.c. power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a.c. signal riding upon the power
supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral compo-
nents below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the desired signal ampli-
tude to the amplitude of the peak spurious spectral compo-
nent, where a spurious spectral component is any signal
present in the output spectrum that is not present at the input
and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first nine
harmonic components to the rms value of the input signal.
THD is calculated as
where F
1 is the RMS power of the fundamental (output)
frequency and f
2 through f10 are the RMS power of the first
9 harmonic frequencies in the output spectrum.
www.national.com
8


Аналогичный номер детали - ADC12040CIVYX

производительномер деталидатащиподробное описание детали
logo
National Semiconductor ...
ADC12040CIVYX NSC-ADC12040CIVYX Datasheet
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Аналогичное описание - ADC12040CIVYX

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