Data Sheet #: TM084
Page 5 of 44
Rev: P02
Date: 12/5/06
© Copyright 200
6 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC4130
Synchronous Clock for SETS
Data Sheet
BUS_AD6
42
I/O
Parallel bus address/data bit6
BUS_AD5
40
I/O
Parallel bus address/data bit5
BUS_AD4
39
I/O
Parallel bus address/data bit4
BUS_AD3
37
I/O
Parallel bus address/data bit3
BUS_AD2
36
I/O
Parallel bus address/data bit2
BUS_AD1
34
I/O
Parallel bus address/data bit1
BUS_AD0
33
I/O
Parallel bus address/data bit0
BUS_INTR
32
O
Interrupt
REF1
2
I
Reference input 1
REF2
4
I
Reference input 2
REF3
5
I
Reference input 3
REF4
8
I
Reference input 4
REF5
10
I
Reference input 5
REF6
12
I
Reference input 6
REF7
14
I
Reference input 7
REF8
16
I
Reference input 8
REF9
17
I
Reference input 9
REF10
19
I
Reference input 10
REF11
21
I
Reference input 11
REF12
23
I
Reference input 12
T0_M/S
24
I
Select master or slave mode for T0, 1: Master, 0: Slave
T4_M/S
28
I
Select master or slave mode for T4, 1: Master, 0: Slave
T0_XSYNC_IN
25
I
Cross-couple SyncLinkTM data link input fot T0 for master/slave redundant applications
T0_XSYNC_OUT
70
O
Cross-couple SyncLinkTM data link output fot T0 for master/slave redundant applications
T4_XSYNC_IN
26
I
Cross-couple SyncLinkTM data link input fot T4 for master/slave redundant applications
T4_XSYNC_OUT
66
O
Cross-couple SyncLinkTM data link output fot T4 for master/slave redundant applications
CLK0_P
85
O
155.52 MHz LVDS output
CLK0_N
86
O
155.52 MHz LVDS output
CLK1
83
O
19.44/38.88/77.76 MHz
CLK2
81
O
19.44/38.88/77.76 MHz
CLK3
79
O
8 KHz frame pulse or 50% duty cycle clock
CLK4
77
O
2 KHz frame pulse or 50% duty cycle clock
CLK5
74
O
44.736/34.368 MHz
CLK6
72
O
1.544/3.088/6.176/12.352/24.704/2.048/4.098/8.192/16.384/32.768 MHZ
CLK7
68
O
1.544/2.048 MHz
Test_Pin
7,11,96
I
Test pin, must be grounded for normal operation
Table 1: Pin Description
Pin Name
Pin #
I/O1
Description