Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 381
Figure 15-13. Slave Command Sequence ............................................................................................ 382
Figure 16-1.
Analog Comparator Module Block Diagram ..................................................................... 407
Figure 16-2.
Structure of Comparator Unit .......................................................................................... 408
Figure 16-3.
Comparator Internal Reference Structure ........................................................................ 409
Figure 17-1.
PWM Module Block Diagram .......................................................................................... 419
Figure 17-2.
PWM Count-Down Mode ................................................................................................ 420
Figure 17-3.
PWM Count-Up/Down Mode .......................................................................................... 421
Figure 17-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 421
Figure 17-5.
PWM Dead-Band Generator ........................................................................................... 422
Figure 18-1.
QEI Block Diagram ........................................................................................................ 456
Figure 18-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 457
Figure 19-1.
Pin Connection Diagram ................................................................................................ 472
Figure 22-1.
Load Conditions ............................................................................................................ 491
Figure 22-2.
I
2C Timing ..................................................................................................................... 493
Figure 22-3.
Hibernation Module Timing ............................................................................................. 494
Figure 22-4.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 495
Figure 22-5.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 495
Figure 22-6.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 496
Figure 22-7.
JTAG Test Clock Input Timing ......................................................................................... 497
Figure 22-8.
JTAG Test Access Port (TAP) Timing .............................................................................. 497
Figure 22-9.
JTAG TRST Timing ........................................................................................................ 497
Figure 22-10. External Reset Timing (RST) .......................................................................................... 498
Figure 22-11. Power-On Reset Timing ................................................................................................. 499
Figure 22-12. Brown-Out Reset Timing ................................................................................................ 499
Figure 22-13. Software Reset Timing ................................................................................................... 499
Figure 22-14. Watchdog Reset Timing ................................................................................................. 499
Figure 23-1.
100-Pin LQFP Package .................................................................................................. 500
9
September 02, 2007
Preliminary
LM3S1968 Microcontroller