10
General-Purpose Timers ................................................................................................. 200
10.1
Block Diagram ........................................................................................................................ 200
10.2
Functional Description ............................................................................................................. 201
10.2.1 GPTM Reset Conditions .......................................................................................................... 202
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 202
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 203
10.3
Initialization and Configuration ................................................................................................. 207
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 207
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 208
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 208
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 209
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 209
10.3.6 16-Bit PWM Mode ................................................................................................................... 210
10.4
Register Map .......................................................................................................................... 210
10.5
Register Descriptions .............................................................................................................. 211
11
Watchdog Timer ............................................................................................................... 236
11.1
Block Diagram ........................................................................................................................ 236
11.2
Functional Description ............................................................................................................. 236
11.3
Initialization and Configuration ................................................................................................. 237
11.4
Register Map .......................................................................................................................... 237
11.5
Register Descriptions .............................................................................................................. 238
12
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 259
12.1
Block Diagram ........................................................................................................................ 260
12.2
Functional Description ............................................................................................................. 260
12.2.1 Transmit/Receive Logic ........................................................................................................... 260
12.2.2 Baud-Rate Generation ............................................................................................................. 261
12.2.3 Data Transmission .................................................................................................................. 262
12.2.4 Serial IR (SIR) ......................................................................................................................... 262
12.2.5 FIFO Operation ....................................................................................................................... 263
12.2.6 Interrupts ................................................................................................................................ 263
12.2.7 Loopback Operation ................................................................................................................ 264
12.2.8 IrDA SIR block ........................................................................................................................ 264
12.3
Initialization and Configuration ................................................................................................. 264
12.4
Register Map .......................................................................................................................... 265
12.5
Register Descriptions .............................................................................................................. 266
13
Synchronous Serial Interface (SSI) ................................................................................ 300
13.1
Block Diagram ........................................................................................................................ 300
13.2
Functional Description ............................................................................................................. 300
13.2.1 Bit Rate Generation ................................................................................................................. 301
13.2.2 FIFO Operation ....................................................................................................................... 301
13.2.3 Interrupts ................................................................................................................................ 301
13.2.4 Frame Formats ....................................................................................................................... 302
13.3
Initialization and Configuration ................................................................................................. 309
13.4
Register Map .......................................................................................................................... 310
13.5
Register Descriptions .............................................................................................................. 311
14
Inter-Integrated Circuit (I2C) Interface ............................................................................ 337
14.1
Block Diagram ........................................................................................................................ 337
5
November 30, 2007
Preliminary
LM3S1960 Microcontroller