List of Figures
Figure 1-1.
Stellaris
® 1000 Series High-Level Block Diagram ............................................................... 27
Figure 2-1.
CPU Block Diagram ......................................................................................................... 35
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 36
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 46
Figure 5-2.
Test Access Port State Machine ....................................................................................... 49
Figure 5-3.
IDCODE Register Format ................................................................................................. 54
Figure 5-4.
BYPASS Register Format ................................................................................................ 55
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 55
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 57
Figure 7-1.
Hibernation Module Block Diagram ................................................................................. 117
Figure 8-1.
Flash Block Diagram ...................................................................................................... 135
Figure 9-1.
GPIO Port Block Diagram ............................................................................................... 160
Figure 9-2.
GPIODATA Write Example ............................................................................................. 161
Figure 9-3.
GPIODATA Read Example ............................................................................................. 161
Figure 10-1.
GPTM Module Block Diagram ........................................................................................ 201
Figure 10-2.
16-Bit Input Edge Count Mode Example .......................................................................... 205
Figure 10-3.
16-Bit Input Edge Time Mode Example ........................................................................... 206
Figure 10-4.
16-Bit PWM Mode Example ............................................................................................ 207
Figure 11-1.
WDT Module Block Diagram .......................................................................................... 236
Figure 12-1.
UART Module Block Diagram ......................................................................................... 260
Figure 12-2.
UART Character Frame ................................................................................................. 261
Figure 12-3.
IrDA Data Modulation ..................................................................................................... 263
Figure 13-1.
SSI Module Block Diagram ............................................................................................. 300
Figure 13-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 302
Figure 13-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 303
Figure 13-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 304
Figure 13-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 304
Figure 13-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 305
Figure 13-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 306
Figure 13-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 306
Figure 13-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 307
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 308
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 309
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 309
Figure 14-1.
I2C Block Diagram ......................................................................................................... 337
Figure 14-2.
I2C Bus Configuration .................................................................................................... 338
Figure 14-3.
START and STOP Conditions ......................................................................................... 338
Figure 14-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 339
Figure 14-5.
R/S Bit in First Byte ........................................................................................................ 339
Figure 14-6.
Data Validity During Bit Transfer on the I2C Bus ............................................................... 339
Figure 14-7.
Master Single SEND ...................................................................................................... 342
Figure 14-8.
Master Single RECEIVE ................................................................................................. 343
Figure 14-9.
Master Burst SEND ....................................................................................................... 344
Figure 14-10. Master Burst RECEIVE .................................................................................................. 345
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 346
November 30, 2007
8
Preliminary
Table of Contents