Pin settings

L6382D5

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2

Pin settings

2.1

Pin connection

Figure 3.

Pin connection (top view)

2.2

Pin description

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

PFI

LSI

HSI

HEI

PFG

N.C.

TPR

GND

LSG

VCC

VREF

CSI

CSO

HEG

N.C.

HVSU

N.C.

OUT

HSG

BOOT

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

PFI

LSI

HSI

HEI

PFG

N.C.

TPR

GND

LSG

VCC

VREF

CSI

CSO

HEG

N.C.

HVSU

N.C.

OUT

HSG

BOOT

Table 1. Pin description

Name

Pin N°

Description

1PFI

Digital input signal to control the PFC gate driver. This pin has to be connected

to a 5V CMOS compatible signal.

2LSI

Digital input signal to control the half-bridge low side driver. This pin has to be

connected to a 5V CMOS compatible signal.

3HSI

Digital input signal to control the half-bridge high side driver. This pin has to be

connected to a 5V CMOS compatible signal.

4HEI

Digital input signal to control the HEG output. This pin has to be connected to a

5V CMOS compatible signal.

5PFG

PFC Driver Output. This pin must be connected to the PFC power MOSFET

gate. A resistor connected between this pin and the power MOS gate can be

used to reduce the peak current. An internal 10K

Ω resistor toward ground

avoids spurious and undesired MOSFET turn-on

The totem pole output stage is able to drive the power MOS with a peak

current of 120mA source and 250mA sink.

6

N.C.

Not connected

7TPR

Input for two point regulator; by coupling the pin with a capacitor to a switching

circuit, it is possible to implement a charge circuit for the Vcc.

8GND

Chip ground. Current return for both the low-side gate-drive currents and the

bias current of the IC. All of the ground connections of the bias components

should be tied to a track going to this pin and kept separate from any pulsed

current return.