DAC7800, 7801, 7802

4

SBAS005A

www.ti.com

DATA

CS

CLK

t

1

t

5

UPD A

UPD B

t

3

t

7

CLR

t

6

t

8

t

4

0V

5V

5V

5V

5V

0V

NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns.

(2) Timing measurement reference level is V + V

2

F

R

IH

IL

.

t

2

PARAMETER

MINIMUM

15ns

15ns

15ns

Update, Data Setup Time

40ns

Update, Data Hold Time

40ns

40ns

40ns

15ns

or UPD B

TIMING CHARACTERISTICS

Data In

Bit 0

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

DAC A

MSB

DAC A

LSB

DAC B

MSB

DAC B

DAC7800 Data Input Sequence

DAC7800 Digital Interface Block Diagram

24-Bit

Shift Register

DAC A Register

UPD A

Data In

CLK

UPD B

LSB

MSB

DAC B Register

LSB

MSB

Bit

23

Bit

12

Bit

11

Bit

0

CLK

DATA INPUT FORMAT