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TPS3103K33DBVT датащи(PDF) 7 Page - Texas Instruments |
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TPS3103K33DBVT датащи(HTML) 7 Page - Texas Instruments |
7 / 23 page www.ti.com PIN DESCRIPTIONS (TOPVIEW) RSTVDD GND MR V DD SENSE TPS3106 DBVPACKAGE RSTSENSE 3 2 4 6 1 5 (TOPVIEW) RESET GND MR V DD PFI TPS3103 DBVPACKAGE PFO 3 2 4 6 1 5 (TOPVIEW) RESET GND MR V DD SENSE TPS3110 DBVPACKAGE WDI 3 2 4 6 1 5 TPS3103xxx TPS3106xxx TPS3110xxx SLVS363E – AUGUST 2001 – REVISED SEPTEMBER 2007 TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME DEVICE NO. GND ALL 2 GND Manual-reset input. Pull low to force a reset. RESET remains low as long as MR is low and for MR ALL 3 the timeout period after MR goes high. Leave unconnected or connect to VDD when unused. PFI TPS3103 4 Power-fail input compares to 0.551 V with no additional delay. Connect to VDD if not used. PFO TPS3103 5 Power-fail output. Goes high when voltage at PFI rises above 0.551 V. TPS3103, RESET 1 Active-low reset output. Either push-pull or open-drain output stage. TPS3110 Active-low reset output. Logic level at RSTSENSE only depends on the voltage at SENSE and RSTSENSE TPS3106 5 the status of MR. Active-low reset output. Logic level at RSTVDD only depends on the voltage at VDD and the RSTVDD TPS3106 1 status of MR. TPS3106, A reset will be asserted if the voltage at SENSE is lower than 0.551 V. Connect to VDD if SENSE 4 TPS3110 unused. VDD ALL 6 Supply voltage. Powers the device and monitors its own voltage. Watchdog timer input. If WDI remains high or low longer than the time-out period, then reset is WDI TPS3110 5 triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling edge. Copyright © 2001–2007, Texas Instruments Incorporated Submit Documentation Feedback 7 |
Аналогичный номер детали - TPS3103K33DBVT |
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Аналогичное описание - TPS3103K33DBVT |
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