LM3S328 Data Sheet
April 27, 2007
7
Preliminary
List of Figures
Figure 1-1.
Stellaris
® High-Level Block Diagram ........................................................................................ 24
Figure 1-2.
LM3S328 Controller System-Level Block Diagram ................................................................... 30
Figure 2-1.
CPU Block Diagram .................................................................................................................. 32
Figure 2-2.
TPIU Block Diagram .................................................................................................................. 33
Figure 5-1.
JTAG Module Block Diagram .................................................................................................... 45
Figure 5-2.
Test Access Port State Machine ............................................................................................... 48
Figure 5-3.
IDCODE Register Format.......................................................................................................... 52
Figure 5-4.
BYPASS Register Format ......................................................................................................... 52
Figure 5-5.
Boundary Scan Register Format ............................................................................................... 53
Figure 6-1.
External Circuitry to Extend Reset............................................................................................. 55
Figure 6-2.
Main Clock Tree ........................................................................................................................ 58
Figure 7-1.
Flash Block Diagram ................................................................................................................. 95
Figure 8-1.
GPIO Module Block Diagram .................................................................................................. 113
Figure 8-2.
GPIO Port Block Diagram........................................................................................................ 114
Figure 8-3.
GPIODATA Write Example...................................................................................................... 115
Figure 8-4.
GPIODATA Read Example ..................................................................................................... 115
Figure 9-1.
GPTM Module Block Diagram ................................................................................................. 151
Figure 9-2.
16-Bit Input Edge Count Mode Example ................................................................................. 155
Figure 9-3.
16-Bit Input Edge Time Mode Example................................................................................... 156
Figure 9-4.
16-Bit PWM Mode Example .................................................................................................... 157
Figure 10-1. WDT Module Block Diagram ................................................................................................... 182
Figure 11-1. ADC Module Block Diagram.................................................................................................... 205
Figure 11-2. Internal Temperature Sensor Characteristic............................................................................ 208
Figure 12-1. UART Module Block Diagram.................................................................................................. 236
Figure 12-2. UART Character Frame........................................................................................................... 237
Figure 13-1. SSI Module Block Diagram...................................................................................................... 271
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer).......................................................... 273
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................................. 274
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................................... 275
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................................. 275
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1........................................................... 276
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0............................... 276
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0....................... 277
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1........................................................... 277
Figure 13-10. MICROWIRE Frame Format (Single Frame)........................................................................... 278
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................................... 279
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements............................ 280
Figure 14-1. I2C Block Diagram ................................................................................................................... 306
Figure 14-2. I2C Bus Configuration.............................................................................................................. 307
Figure 14-3. Data Validity During Bit Transfer on the I2C Bus..................................................................... 307
Figure 14-4. START and STOP Conditions ................................................................................................. 307
Figure 14-5. Complete Data Transfer with a 7-Bit Address ......................................................................... 308
Figure 14-6. R/S Bit in First Byte ................................................................................................................. 309
Figure 14-7. Master Single SEND................................................................................................................ 310
Figure 14-8. Master Single RECEIVE.......................................................................................................... 311
Figure 14-9. Master Burst SEND (sending n bytes)..................................................................................... 312
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